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? document? number: ? anx \ 7150 \ 0410 ? ? ? ? ANX7150 ? ultra \ low ?power?hdmi ? tm ?transmitter ? ? programmer ? guide ?? revision ? 0.93 ? september ? 2009 ? santa ? clara, ? ca ? 95054, ? usa ? (408) ? 988 \ 8848 ? www.analogix.com ? analogix ? semiconductor, ? inc. 3211 ? scott? blvd., ? suite ? 102 ? free datasheet http:///
? preliminary programmer guide contents ? ? 1 introduction ? .............................................................................................. ? 5 2 firmware ? overview ? ................................................................................... ? 6 2.1 firmware? ? ? ? 3 initialization ? ............................................................................................... ? 8 4 wait ? hotplug? ............................................................................................. ? 9 5 read? and ? parse ? edid ? ................................................................................ ? 10 6 configure ? video ? ....................................................................................... ? 11 6.1 video? ? ? ? 6.2 color ? ? ? ? \ ? ? 6.3 pixel? ? ? ? ? ? 6.4 register ? ? ? ? ? ? ? 6.5 register ? ? ? ? ? ? 7 configure ? audio ? ....................................................................................... ? 15 7.1 audio ? ? ? ? ? ? ? ? 7.2 spdif ? ? ? ? ? ? ? ? 7.3 i2s ? ? ? ? 7.4 super ? ? ? ? ? 7.5 audio ? ? ? ? 8 configure ? auxiliary ? information ? packets? .................................................. ? 17 9 hdcp ? authentication ? ............................................................................... ? 20 10 playback ? .................................................................................................. ? 22 11 interrupt? process ? ..................................................................................... ? 22 ? ? ??????????????????????????????? ? ????????????????????????? ? ? ? ? free datasheet http:///
? preliminary programmer guide ? page ? 3 ? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? list ? of ? figures ? ? figure ? 1 \ 1 ?? digital ? multimedia ? display ? system ? with ? hdmi ? interface ? ...................................................................... ? 5 figure ? 2 \ 1 ?? state ? diagram ? of ? the ? ANX7150 ? firmware? ............................................................................................. ? 6 figure ? 5 \ 1 ?? read ? and ? parse ? edid ? flowchart ? .......................................................................................................... ? 10 figure ? 6 \ 1 ?? video ? configuration ? flowchart ? ........................................................................................................... ? 11 figure ? 7 \ 1 ?? audio ? configuration ? flowcharts ? ......................................................................................................... ? 15 figure ? 8 \ 1 ?? infoframe ? packets ? configuration ? flowchart ? ....................................................................................... ? 19 figure ? 9 \ 1 ??? initialization ? of ? hdcp ? authentication ? ............................................................................................... ? 20 figure ? 9 \ 2 ?? hardware? hdcp ? authentication ? flowchart ? ........................................................................................ ? 21 figure ? 11 \ 1 ?? interrupt ? process ? flowchart ? (1) ? ........................................................................................................ ? 22 figure ? 11 \ 2 ??? interrupt ? process ? flowchart ? (2) ? ...................................................................................................... ? 23 figure ? 11 \ 3 ?? interrupt ? process ? flowchart ? (3) ? ........................................................................................................ ? 23 figure ? 11 \ 4 ?? interrupt ? process ? flowchart ? (4) ? ........................................................................................................ ? 24 ? ? ? ? list ? of ? tables ? ? table ? 3 \ 1 ?? register ? settings ? for ? ANX7150 ? initialization? .......................................................................................... ? 9 table ? 7 \ 1 ?? value ? of ? the ? register ? inv_aud_clk ? and ? mclk_phs_ctrl ? ................................................................. ? 16 table ? 8 \ 1 ?? avi ? infoframe? location ? ......................................................................................................................... ? 17 table ? 8 \ 2 ?? audio ? infoframe?s ? location ? ................................................................................................................... ? 17 ? ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 4 ? of ? 25? preliminary programmer guide revision? history? ? ? ? ? ? ? 0.9 ? may ? 2009 ?? initial ? version.? 0.92? july ? 2009 ?? 1. delete ? appendix ? in ? chapter ? 12 ? and ? 13. ? 2. ??add? the ? description ? of ? achieving ? lower ? stand \ by ? power ? in ? ? , ? ? ? , ? chapter ? 2.? 0.93? sept ? 2009 ?? 1. update ? description ? of ? initialization ? in ? chapter ? 3. ? 2. update ? description ? of ? read ? and ? parse ? edid ? in ? chapter ? 5. ? ? free datasheet http:///
? ? page ? 5 ? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide ? 1 introduction? the? ANX7150 ? is ? an ? hdmi ? (high \ definition ? multimedia ? interface) ? transmitter ? device ? supporting ? hdmi ? 1.2 ? and ? hdcp ? 1.1 ? specifications. ? the ? ANX7150 ? can ? be ? used ? to ? send ? protected ? digital ? video ? and ? audio ? data. ? it ? provides ? a? low? cost ? digital ? interface ? for ? source ? devices ? such ? as ? dvd ? players, ? set \ top ? boxes, ? dvrs, ? computers, ? and ? so ? on. ? it ? is ? also ? backward ? compatible ? with ? dvi ? 1.0 ? and ? supports ? any ? dvi ? 1.0 ? display ? connected ? with ? the ? ANX7150. ? this ? document ? is ? a? description ? of ? the ? firmware ? of ? the ? ANX7150 ? evaluation ? board ? and ? a? guide ? for ? system ? engineers ? and ? programmers. ? figure ? 1 \ 1 ? illustrates? the ? connection ? of ? a? hdmi ? transmitter ? and ? receiver ? in ? a? digital ? multimedia ? display ? system. ? ? ? figure ? 1\ 1?? digital? multimedia ? display ? system ? with ? hdmi ? interface ? ? ? ? ? ? ? ? ? ? ? ? ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 6 ? of ? 25? preliminary programmer guide 2 firmware ?overview ? the? top ? level ? state ? diagram ? of ? the ? ANX7150 ? firmware? is ? shown ? in ? figure ? 2 \ 1. ? initialization (mcu, 7150) (1) playback (8) hdcp authentication (7) config audio (5) config video (4) read&parse edid (3) wait hotplug (2) hotplug detected edid parse done hdmi mode audio stable fail <10 times fail for 10 times success initial done video not satble audio not stable unplug video mode change config packets (6) packet config done ri, pj check fail dvi mode audio mode change any state (except 1) any state (except 1,2,3) any state (except 1,2,3,4) 1: initialization 2: wait hotplug 3: read&parse edid 4: config video 5: config audio 6: config packets 7: hdcp authentication 8: playback send blue screen ? ? \ ?? ? ? ? ? ? ? a ? total ? of ? eight ? states ? are ? specified ? in ? the ? ANX7150 ? firmware? state ? machine. ? ? in ? the ? initialization ? state, ? the ? firmware ? sets ? necessary ? registers ? of ? the ? ANX7150 ? to ? an ? appropriate ? value ? for ? the ? operating ? mode. ? in ? this ? state, ? the ? ANX7150 ? is ? in ? a? power ? down ? status, ? only ? idck, ? mclk, ? sck ? and ? the? hotplug ? module ? are ? active. ? ? ? after ? the ? ANX7150 ? is ? initialized, ? the ? firmware ? enters ? the ? wait ? hotplug ? state.? in ? this ? state, ? when ? a? hotplug ? state ? is ? detected ? (an ? active ? hdmi ? receiver ? is ? plugged ? in),? the ? ANX7150 ? powers ? on ? and ? enters ? into? a? read ? & ? parse ? edid ? state. ? this ? is ? a? stand \ by ? state ? of ? ANX7150, ? to ? achieve ? low? power ? consumption ? in ? stand \ by ? mode, ? all? the ? functions ? of ? ANX7150 ? shall? be ? power ? down, ? except ? the ? i2c ? slave ? interface.? it ? is ? recommended ? that ? the ? av ? source ? (soc) ? shall? stop ? sending ? video/audio ? to ? ANX7150 ? in ? stand \ by ? mode ? to ? achieve? even ? lower? stand \ by ? power.? ? ? ? ? in ? this ? state, ? the ? firmware ? reads ? and ? parses ? the ? edid ? data ? of ? the ? receiver ? through ? the ? ddc ? channel. ? based ? on ? the ? parsing ? results, ? the ? transmitter ? selects ? a? preferred ? video/audio ? mode ? to ? send. ? free datasheet http:///
? ? page ? 7 ? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide config ? video: ? the? firmware? configures ? the ? video ? format ? such ? as ? color ? space, ? de ? generator, ? embedded ? sync, ? pixel? clock ? repeat? times, ? and ? so ? on. ? config ? audio: ? the? firmware? configures ? the ? audio ? format ? such? as ? audio ? source ? (i2s, ? spdif, ? and ? one ? bit ? audio), ? audio ? fifo ? map, ? audio ? data? down ? sample, ? audio ? channel ? status, ? and ? so ? on. ? some ? audio ? configuration ? contents ? are ? specified ? by ? the ? system. ? config ? packets: ? the? firmware ? then ? configures ? infoframe? packets ? such ? as ? avi ? infoframe, ? audio ? infoframe, ? spd ? infoframe, ? and ? so ? on.? some ? contents ? of ? infoframe ? packets ? are ? specified ? by ? the ? system. ? hdcp ? authentication: ? in ? this ? state, ? the ? firmware ? handles ? hdcp ? authentication, ? including ? hdcp ? error ? handling. ? playback: ? this ? is ? the ? normal ? work ? mode ? of ? the ? system. ? the ? firmware? monitors? related ? status ? registers ? and ? responses ? to ? interrupts, ? and ? then ? takes ? corresponding ? action. ? 2.1 firmware ? main ? loop ? the? following ? program ? is ? the ? main ? loop ? of ? the ? ANX7150 ? firmware. ?? while ? (1) ?? { ? ???????? if ? (restart_system) ? { ? ???????????? debug_puts("restart ? system..."); ? ???????????? restart_system ? = ? 0; ? ?? ??????? ANX7150_initial(); ? ???????? } ? ???????? if ? (!debug_mode) ?? ???????? { ? ?? ?????? ANX7150_interrupt_process(); ? ??????????? ANX7150_timer_process(); ? ???????? } ? ???????? commandprocess ? (); ? ???????? delay_ms(5); ? } ? after ? ANX7150 ? initialization ? is ? done, ? the ? firmware ? runs ? in ? the ? loop ? of ? ANX7150_interrupt_process( ? ), ? timerprocess( ? ) ? and ? commandprocess( ? ). ? ANX7150_interrupt_process( ? ) ? monitors? the ? ANX7150 ? interrupt ? events ? and ? calls ? the ? corresponding ? service ? routines ? for ? processing. ? ANX7150_timer_process( ? ) ? includes? a? scheduler ? that ? divides ? pending ? tasks ? into? four ? time ? slots ? (ANX7150_timer_slot1, ? ANX7150_timer_slot2, ? ANX7150_timer_slot3, ? ANX7150_timer_slot4). ? each ? slot ? lasts? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 8 ? of ? 25? preliminary programmer guide about ? 8ms. ? slot ? times ? are ? defined ? as ? follows: ? ANX7150_timer_slot1 ? is ? for ? hpd ? detection, ? edid ? reading ? and ? parsing; ? ANX7150_timer_slot2 ? is ? for ? video/audio/packet ? configuration; ? ANX7150_timer_slot3 ? is ? for ? hdcp ? process; ? ANX7150_timer_slot4 ? is ? for ? future ? usage.? command ? process( ? ) ? is ? for ? debug ? purposes. ? 3 initialization ? power \ on ? reset : ? the ? resetn ? input ? to ? the ? ANX7150 ? is ? commonly ? connected ? to ? a ? general ? purpose ? input/output ? (gpio) ? pin ? of ? the ? host ? microcontroller. ?? firmware? is ? responsible ? for ? generating ? the ? hardware? reset? signal ? of ? the ? ANX7150 ? by ? pulling ? down ? resetn ? for ? a? minimum ? of ? 2ms. ? locate ? ANX7150: ? after ? asserting ? resetn, ? the ? firmware? should ? ensure ? it ? has ? established ? communications ? with ? the ? ANX7150 ? by ? confirming ? that ? it ? can ? read ? its ? vendor ? and ? device ? id ? registers. ? the? following ? program ? describes ? the ? ANX7150 ? reset ? and ? locates ? process. ? for ? (i=0; ? i<10; ? i++) ? ???????? { ? ???????????? ANX7150_resetn_pin ? = ? 0; ? ???????????? delay_ms(2); ? ???????????? ANX7150_resetn_pin ? = ? 1; ? ???????????? delay_ms(2); ? ? ???????????? c ? = ? ANX7150_i2c_read_p0_reg(ANX7150_dev_idl_reg, ? &d1); ? ???????????? if ? (c)? continue; ? ? ???????????? c ? = ? ANX7150_i2c_read_p0_reg(ANX7150_dev_idh_reg, ? &d2); ? ???????????? if ? (c)? continue; ? ? ???????????? if ? (d1 ? ==? 0x50? &&? d2 ? ==? 0x71) ?? ???????????? { ? ???????????????? debug_puts("ANX7150 ? detected!"); ? ???????????????? return ? 1; ? ???????????? } ? ???????? } ? ???????? debug_puts("device ? not ? detected"); ? free datasheet http:///
? ? page ? 9 ? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide ???????? return ? 0; ? register ? initialization : ? after ? power\ on ? reset, ? most ? of ? the ? ANX7150 ? device ? functions? are ? powered ? down ? except ? for ? pixel? clock ? detection ? and ? hot ? plug ? detection. ? the? firmware ? then ? needs ? to ? configure ? the ? other ? registers ? appropriately ? for ? system ? operation. ? table ? 3 \ 1 ? lists? the ? ANX7150 ? register ? functions ? involved ? in ? the ? initialization ? sequence. ? table ? 3\ 1??register ? settings ? for ? ANX7150 ? initialization ? register ? offset ? register ? name ? initialized ? vale ? purpose ? 0x72: ? 0x45? intr ? mask ? 1? 0x04?? 0x72: ? 0x46? intr ? mask ? 2? 0x00?? 0x72: ? 0x47? intr ? mask ? 3? 0x00?? 0x72: ? 0x9a ? chip ? control ? reg ? set ? bit? 0? to ? 0? enable ? auto ? set ? clock ? range ? for ? video ? pll ? 0x72: ? 0xcc? hdcp_bluescreen0_reg 0x10? initialize ? the ? register ? value ? of ? blue ? screen. ? when ? hdcp ? fails, ? the ? ANX7150 ? sends ? the ? blue ? screen ? pattern. ? the ? initialization ? value ? is ? for ? a ? green ? field ? in ? rgb ? mode. ? 0x72: ? 0xcd ? hdcp_bluescreen1_reg 0xeb ? 0x72: ? 0xce ? hdcp_bluescreen2_reg 0x10? 4 wait ?hotplug ? in ? wait ? hotplug ? state, ? the ? chip ? is ? in ? a ? power ? down ? mode. ? the ? system ? only ? responds ? to ? hotplug ? change ? interrupt. ? when ? a? hotplug ? interrupt ? is ? detected ? in ? the ? interrupt ? routine, ? the ? firmware? determines ? whether ? the ? interrupt ? is ? a? receiver ? plug \ in ? or ? a? un \ plug. ? if ? the ? interrupt ? is ? a? plug \ in, ? the ? chip ? is ? powered ? on, ? and ? the ? system ? is ? set ? to ? read ? and ? parse ? edid. ? ? ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 10 ? of ? 25 ? preliminary programmer guide 5 read ?and ?parse ?edid ? ? figure ? 5\ 1?? read ? and ? parse ? edid ? flowchart ? ? figure ? 5 \ 1 ? illustrates? edid ? parsing. ? reading ? the ? edid ? content ? from ? the ? eeprom ? of ? the ? receiver ? across? the ? ddc ? channel ? is ? a ? simple ? process. ? all ? the ? edid ? data ? bytes ? can ? be ? read ? into? a ? mcu ? local ? ram ? at? one ? time ? (enhanced ? ddc ? sequential ? read), ? or ? read ? piece ? by ? piece ? (sequential ? byte ? read) ? and ? then ? parsed ? on ? the ? fly. ? for ? the ? purpose ? of ? saving ? into ? mcu ? ram ? space, ? parsing ? the ? edid ? contents ? is ? a? complex ? process. ? basically, ? two ? fields ? are ? important ? in ? parsing ? the ? edid: ? the ? hdmi ? or ? dvi ? mode ? (in ? the ? ?vender ? specific? ? tag ? byte ? data? area? on ? extension ? block ? #1, ? hdmi ? identifier=0x000c03), ? and ? the ? support ? capability ? of ? ycbcr ? (byte ? address ? 0x03 ? on ? extension ? block ? #1). ? this ? edid ? information ? must ? be ? properly ? transferred ? from ? the ? receiver. ? ? ? free datasheet http:///
? ? page ? 11? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide 6 configure?video ? start config video input video clk detected unmute tmds set avmute get rx supported video format from edid tx support mode[i] more modes? select mode[i] select640x480 generate de? config de generator 656? config embedded sync config color space (dvi) config up/down sample (dvi) config pixel repeat and clock divide config input bus format hdmi mode? to config audio state to hdcp authentication state return dvi hdmi y y y y y n n n n n config blue screen ? ? \ ?? ? ? ? figure ? 6 \ 1 ? illustrates? the ? basic ? video ? configuration ? process. ?? at ? the ? beginning ? of ? video ? configuration, ? the ? firmware? initializes ? the ? blue ? screen ? registers ? according ? to ? the ? video ? format ? (rgb, ? ycbcr4:4:4 ? or ? ycbcr4:2:2). ? if ? hdcp ? authentication ? fails, ? the ? firmware? terminates ? hdcp ? encryption ? and ? enables ? the ? blue ? screen ? output ? instead ? of ? normal ? video ? output. ? after ? the ? input ? pixel? clock ? is ? detected, ? the ? firmware ? un \ mutes ? the ? tmds ? link ? (register ? 0x72:0x99, ? bit ? 7) ? and ? sets ? avmute. ?? based ? on ? the ? parsing ? result ? of ? edid ? and ? the ? capability ? of ? the ? video ? source, ? the ? transmitter ? selects ? a? preferred ? video ? format ? to ? send. ? if ? required, ? de ? generator, ? embedded ? sync, ? color ? space, ? and ? pixel? up \ sample ? are ? configured. ?? if ? hdmi ? mode ? is ? selected, ? the ? firmware? goes ? to ? the ? config ? audio ? state. ?? if ? dvi ? mode ? is ? selected, ? the ? firmware ? goes ? to ? the ? hdcp ? authentication ? state ? without ? config ? video ? and ? config ? packets. ? a ? number ? of ? difference ? video ? formats ? are ? supported ? by ? the ? ANX7150 ? chip. ? the? supported ? video ? formats ? are ? listed ? in ? the ? hdmi ? transmitter ? design ? specification.? based ? on ? the ? configuration ? process ? of ? video, ? the ? video ? interface ? format ? is ? configured ? by ? the ? controller ? writing ? to ? the ? following ? registers.? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 12 ? of ? 25 ? preliminary programmer guide 6.1 video ? format ? capture ? z rgb and ycbcr 4:4:4 formats with separate syncs (24 r bpp mode) ? z ycbcr 4:2:2 formats with separate syncs ? z ycbcr 4:2:2 formats with embedded syncs ? setting ? emb_sync_mode ? bit \ 6 ? of ? video ? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? de \ embedded ? sync. ? z yc mux 4:2:2 formats with separate sync configure ? vid_yc_bit_sel ? bit \ 3 ? of ? video ? control? register ? (0x72:0x12) ? and ? demux_yc_en ? bit \ 5 ? of ? video? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? yc \ mux ? 4:2:2 ? formats? with ? bit \ mapping ? options. ? ? bit r mapping option 1 bit r mapping option 2 vid_yc_bit_sel ? 0x0? 0x1? ? z yc mux 4:2:2 with embedded sync ? setting ? emb_sync_mode ? bit \ 6 ? of ? video ? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? de \ embedded ? sync. ? configure ? vid_yc_bit_sel ? bit \ 3 ? of ? video ? control? register ? (0x72:0x12) ? and ? demux_yc_en ? bit \ 5 ? of ? video? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? yc \ mux ? 4:2:2 ? formats? with ? bit \ mapping ? options. ? ? bit r mapping option 1 bit r mapping option 2 vid_yc_bit_sel ? 0x0? 0x1? ? z 12r bit rgb and ycbcr 4:4:4 ddr formats with separate syncs (24 r bpp) ? setting ? dv_bus_mode ? bit \ 3 ? of ? video ? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? dual \ data \ rate ? (ddr) ? mode.? ? z 12r bit rgb and ycbcr 4:4:4 ddr formats with separate syncs (18 r bpp) ? setting ? dv_bus_mode ? bit \ 3 ? of ? video ? capture ? control ? register ? #0 ? (0x72:0x13) ? to ? enable ? dual \ data \ rate ? (ddr) ? mode.? 6.2 color ? space ? convert ? and ? up - sample ? when ? the ? input ? video ? data? are ? ycbcr? 4:4:4 ? for ? dvi ? mode, ? color ? space ? convert ? configuration ? is ? necessary. ? set ? cspace_y2r ? of ? video ? mode ? register ? (0x72:0x11) ? bit \ 4 ? to ? enable ? the ? color ? space ? converter. ? when ? the ? input ? video ? data ? are ? ycbcr? 4:2:2 ? for ? dvi ? mode, ? color ? space ? convert ? and ? up \ sample ? must ? be ? set. ? set? up_sample ? of ? video? mode ? register ? (0x72:0x11) ? bit \ 2 ? to ? enable ? up \ sample. ? range_y2r ? and ? y2r_sel ? are ? used ? for ? color ? space ? convert. ? free datasheet http:///
? ? page ? 13? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide 6.3 pixel ? repeat ? and ? clock ? divide ? there? is ? a? video ? fifo ? with ? 4 ? * ? 3 ? bytes ? size ? to ? convert ? video ? data? from ? idck ? to ? hdmi ? link ? clock? domain. ? this ? fifo ? also ? can? perform ? pixel? repetition ? and ? clock ? divide ? for ? some ? combinations ? of ? video ? input ? clock ? frequency ? and ? audio ? sampling ? rate. ? the? value? of ? pixel? repetition ? is ? determined ? by ? the ? input ? video ? clock ? frequency ? and ? link ? pixel? data ? clock? frequency. ? in_pixel_rpt ? (0x72:0x11 ? bits ? 0, ? 1), ? tr_pixel_rpt? (0x72:0x12 ? bits ? 0, ? 1)? and ? demux_yc_en ? (0x72:0x13 ? bit ? 5) ? must ? be ? set ? properly ? and ? reflect ? the ? format ? relationship ? of ? input ? video ? data ? and ? output ? link ? data. ? 6.4 ? register ? set ? for ? embedded ? sync ? decode ? when ? input ? video ? stream ? is ? embedded ? sync ? encoded, ? the ? emb_sync_mode ? (0x72:0x13 ? bit \ 6) ? should ? be ? configured ? with ? 1. ? to ? decode ? embedded ? sync ? correctly, ? the ? following ? registers ? must ? be ? configured: ? a) vsync_pol ? (0x72:0x14 ? bit \ 6) ? b) hsync_pol ? (0x72:0x14 ? bit \ 5) ? c) vsync_fp_line ? (0x72:0x23) ? d) vsync_act_wid_line ? (0x72:0x24) ? e) vh_fp_low(0x72:0x19) ? vh_fp_high ? (0x72:0x1a) ? horizon_front_porch ? f) hsync_width ? (0x72:0x1b ? and ? 0x72:0x1c) ? horizon_sync_width ? g) inv_fld_pol ? (0x72:0x14 ? bit \ 4)? invert_field_polarity ? (optional) ? 6.5 register ? set ? for ? de ? generator ? when ? the ? user ? wants ? to ? re\ generate ? the ? de ? signal, ? the ? de_gen_en ? (0x72:0x13 ? bit \ 7) ? should ? be ? configured ? with ? 1. ? to ? re\ generation ? the ? de ? signal ? correctly, ? the ? following ? registers ? must ? be ? configured: ? 1. vsync_pol ? (0x72:0x14 ? bit \ 6) ? 2. hsync_pol ? (0x72:0x14 ? bit \ 5) ? 3. act_line ? (0x72:0x21 ? and ? 0x72:0x22) ? active_lines? 4. vv_res ? (0x72:0x1f ? and ? 0x72:0x20) ? total_lines? 5. vsync_act_wid_line ? (0x72:0x24) ? 6. vsync_bp_line ? (0x72:0x25) ? vertical_back_porch ? 7. act_pix ? (0x72:0x17 ? and ? 0x72:0x18) ? active_pixels ? 8. vh_res_low ? and ? vh_res_high ? (0x72:0x15 ? and ? 0x72:0x16) ? total_pixels ? 9. hsync_width ? (0x72:0x1b ? and ? 0x72:0x1c) ? horizon_sync_width ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 14 ? of ? 25 ? preliminary programmer guide 10. vh_bp_low ? and ? vh_bp_high ? (0x72:0x1d ? and ? 0x72:0x1e) ? horizon_back_porch ? 11. video_type ? (0x72:0x14 ? bit \ 3) ? the? video ? register ? set ? from ? 0x72:0x26 ? to ? 0x72:0x36 ? is ? used ? by ? the ? firmware ? to ? check ? the ? input ? video ? format ? parameters. ? ? note: ? after ? configuring ? the ? corresponding ? video ? registers, ? the ? firmware? should ? set ? vid_in_en ? of ? video ? control? register ? (0x72:0x12 ? bit \ 4)? to ? turn ? on ? video ? capture ? input. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? free datasheet http:///
? ? page ? 15? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide 7 configure?audio ? as ? figure ? 7 \ 1 ? illustrates, ? the ? ANX7150 ? supports ? three ? audio ? input ? formats ? including ? spdif, ? i 2 s,? and ? super ? audio. ?? audio ? source ? select: ? at ? the ? beginning ? of ? audio ? configuration, ? the ? firmware? must ? select ? the ? audio ? source ? by ? setting ? audio ? control? register#1(0x72: ? 0x51). ? ? config audio select source select mclk as source enable spdif check interrupt 72, 44, (7,0) adjust mclk phase down sample down sample select sck as source config i2s channel config i2s format map i2s fifo down sample down sample select sck as source enable stream[0:5] map stream config i2s channel status (5 regs) audio layout 72, 50, 7 audio enable 72, 51, 7 return spdif one bit audio i2s n y n y ? ? figure ? 7\ 1??audio ? configuration ? flowcharts ? ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 16 ? of ? 25 ? preliminary programmer guide 7.1 audio ? clock ? source ? select? for ? cts ? generation ? the? ANX7150 ? can? support ? mclk ? and ? sck ? (64*f s ) ? for ? cts ? generation. ? configure ? cts_ ? gen_sc ? to ? select ? the ? cts ? generation ? source ? clock. ? when ? using ? mclk, ? the ? firmware? needs ? to ? configure ? freq_mclk ? of ? register ? hdmi ? audio ? control ? register ? #0 ? (0x72:0x50). ? 7.2 spdif ? format? configure ? and ? clock ? phase ? control? because ? the ? input ? mclk ? phase ? is ? uncertain ? with ? spdif ? data, ? the ? firmware ? needs ? to ? check ? the ? spdif_err, ? spdif_bi_phase_err, ? and ? spdif_unstbl ? interrupts ? status. ? if ? a? spdif ? error ? is ? detected, ? the ? firmware? should ? configure ? the ? register ? inv_aud_clk ? (0x72:0x50 ? bit \ 3)? and ? mclk_phs_ctrl ? (0x72:0x52 ? bit ? 5 ? and ? bit ? 6) ? with ? the ? following ? values. ? table ? 7\ 1?? value ? of ? the ? register ? inv_aud_clk ? and? mclk_phs_ctrl ? freq_mclk ? inv_aud_clk ? mclk_phs_ctrl ? 128*fs ? 1?b1 ? n/a ? 256*fs ? n/a ? 2?b01? 384*fs ? n/a ? 2?b01? or ? 2?b10 ? 512*fs ? n/a ? 2?b10? when ? using ? the ? spdif ? as ? input ? audio ? source, ? the ? firmware? should? read ? the ? fs_freq ? and ? word_size ? from ? input ? audio ? spdif ? channel ? status ? register ? (0x72:0x55). ? if ? the ? value? of ? fs_freq ? is ? not ? correct, ? the ? firmware ? should ? configure ? fs_freq ? of ? audio ? i2s ? channel ? status ? register ? #4 ? (0x72:0x59) ? with ? the ? correct ? value? and ? set ? spdif_fs_ovrwr ? of ? hdmi ? audio ? control ? register ? #1 ? (0x72:0x51). ? 7.3 i2s ? format ? configure ? when ? selecting ? the ? i 2 s ? input ? source, ? the ? firmware? should? configure ? i 2 s ? format? control? register ? (0x72:0x52) ? and ? i 2 s ? channel ? status ? register ? 1 ? to ? register ? 5. ? the ? i 2 s ? capture ? block ? decodes ? the ? input ? audio ? data ? based ? on ? settings ? of ? shift_ctrl, ? dir_ctrl, ? ws_pol ? and ? just_ctrl ? of ? register ? 0x72:0x52. ? 7.4 super ? audio ? configure ? (tbd) ? 7.5 audio ? down ? sample ? the? ANX7150 ? supports ? audio ? down ? sample ? 2 \ to \ 1 ? or ? 4 \ to \ 1. ? when ? the ? sample ? frequency ? of ? input ? audio ? needs ? to ? be ? reduced, ? the ? firmware? should ? configure ? aud_down_smpl ? of ? hdmi ? audio ? control ? register ? #0 ? (0x72:0x50). ? if ? the ? audio ? source ? is ? spdif, ? the ? firmware? should ? also ? configure ? fs_freq ? and ? spdif_fs_ovrwr. ? after ? selecting ? the ? input ? audio ? source, ? the ? firmware ? should? configure ? the ? hdmi_aud_layout ? of ? hdmi ? audio ? control? register ? #0 ? (0x72:0x50 ? bit \ 7) ? based ? on ? the ? audio ? channel? number. ? after ? configuring ? the ? corresponding ? audio ? registers, ? the ? firmware? should ? set ? aud_in_en ? of ? hdmi ? audio ? control ? register ? #1 ? (0x72:0x51 ? bit \ 7) ? to ? enable ? audio ? data? path. ? free datasheet http:///
? ? page ? 17? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide 8 configure?auxiliary? information ? packets ? the? detailed ? auxiliary ? information ? carried ? from ? source ? to ? dtv ? monitor ? is ? described ? in ? the ? hdmi ? 1.1 ? specification ? (section ? 8) ? and ? eia/cea \ 861c ? specification ? (section6). ?? note: ? in ? ANX7150 ? firmware? rev. ? 1.0, ? only ? avi ? infoframe ? and ? audio ? infoframe ? are ? implemented. ? the ? vender ? specific, ? mpeg ? source, ? acp, ? isrc1, ? isrc2 ? infoframe ? will ? be ? added ? in ? the ? firmware? future ? release. ? the? avi ? infoframe ? location ? in ? the ? ANX7150 ? is ? showed ? in ? table ? 8 \ 1. ? table ? 8\ 1??avi ? infoframe ? location ?? register ? address ? name ? type ? default ? description ? 0x7a:0x00 ? avi_hb0 ? (type) ? r/w ? 0x00? type ? 0x7a:0x01 ? avi_hb1 ? (version) ? r/w ? 0x00? version ? 0x7a:0x02 ? avi_hb2 ? (length) ? r/w ? 0x00? length ? 0x7a:0x03 ? avi_pb0 ? r/w ? 0x00? checksum ? 0x7a:0x04 ? avi_pb1 ? r/w ? 0x00? avi ? data ? byte ? 1 ? 0x7a:0x05 ? avi_pb2 ? r/w ? 0x00? avi ? data ? byte ? 2 ? 0x7a:0x06 ? avi_pb3 ? r/w ? 0x00? avi ? data ? byte ? 3 ? 0x7a:0x07 ? avi_pb4 ? r/w ? 0x00? avi ? data ? byte ? 4 ? 0x7a:0x08 ? avi_pb5 ? r/w ? 0x00? avi ? data ? byte ? 5 ? 0x7a:0x09 ? avi_pb6 ? r/w ? 0x00? avi ? data ? byte ? 6 ? 0x7a:0x0a? avi_pb7 ? r/w ? 0x00? avi ? data ? byte ? 7 ? 0x7a:0x0b ? avi_pb8 ? r/w ? 0x00? avi ? data ? byte ? 8 ? 0x7a:0x0c ? avi_pb9 ? r/w ? 0x00? avi ? data ? byte ? 9 ? 0x7a:0x0d ? avi_pb10 ? r/w ? 0x00? avi ? data ? byte ? 10 ? 0x7a:0x0e ? avi_pb11 ? r/w ? 0x00? avi ? data ? byte ? 11 ? 0x7a:0x0f? avi_pb12 ? r/w ? 0x00? avi ? data ? byte ? 12 ? 0x7a:0x10 ? avi_pb13 ? r/w ? 0x00? avi ? data ? byte ? 13 ? 0x7a:0x11 ? avi_pb14 ? r/w ? 0x00? avi ? data ? byte ? 14 ? 0x7a:0x12 ? avi_pb15 ? r/w ? 0x00? avi ? data ? byte ? 15 ? ? the? audio ? infoframe ? location ? in ? ANX7150 ? is ? showed ? in ? table ? 8 \ 2. ? table ? 8\ 2?? audio ? infoframe?s ? location ? register ? address ? name ? type ? default ?? description ? 0x7a:0x20 ? audio_hb0? (type) ? r/w ? 0x00? audio? infoframe ? packet ? type. ? 0x7a:0x21 ? audio_hb1? r/w ? 0x00? version ? 0x7a:0x22 ? audio_hb2? r/w ? 0x00? length ? 0x7a:0x23 ? audio_pb0? r/w ? 0x00? checksum ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 18 ? of ? 25 ? preliminary programmer guide 0x7a:0x24 ? audio_pb1? r/w ? 0x00? audio? infoframe ? data ? byte ? 1 ? 0x7a:0x25 ? audio_pb2? r/w ? 0x00? audio? infoframe ? data ? byte ? 2 ? 0x7a:0x26 ? audio_pb3? r/w ? 0x00? audio? infoframe ? data ? byte ? 3 ? 0x7a:0x27 ? audio_pb4? r/w ? 0x00? audio? infoframe ? data ? byte ? 4 ? 0x7a:0x28 ? audio_pb5? r/w ? 0x00? audio? infoframe ? data ? byte ? 5 ? 0x7a:0x29 ? audio_pb6? r/w ? 0x00? audio? infoframe ? data ? byte ? 6 ? 0x7a:0x2a? audio_pb7? r/w ? 0x00? audio? infoframe ? data ? byte ? 7 ? 0x7a:0x2b ? audio_pb8? r/w ? 0x00? audio? infoframe ? data ? byte ? 8 ? 0x7a:0x2c ? audio_pb9? r/w ? 0x00? audio? infoframe ? data ? byte ? 9 ? 0x7a:0x2d ? audio_pb10? r/w ? 0x00? audio? infoframe ? data ? byte ? 10 ? ? figure ? 8 \ 1 ? illustrates? infoframe ? packets ? configuration. ? when ? processing ? a? new ? packet, ? the ? firmware? gets ? the ? packet ? type ? and ? determines ? whether ? it ? is ? a? new ? packet ? or ? not.? if ? a? new ? packet ? comes, ? according ? to ? the ? packet ? type, ? the ? firmware ? disables? the ? transmission ? enable ? bit ? and ? repeat ? bit ? of ? this ? kind ? of ? packet ? in ? the ? infoframe ? packet? control ? register ? 1 ? (0x7a:0xc0). ? for ? example, ? if ? a ? new? avi ? infoframe ? packet ? is ? received, ? the ? firmware? should ? disable ? bit ? 4 ? and ? bit ? 5. ? then, ? the ? firmware? configures ? the ? packet ? type, ? version, ? length ? and ? calculates ? the ? checksum. ? after ? the ? packet ? has ? been ? loaded ? to ? the ? registers, ? the ? firmware ? enables ? the ? corresponding ? enable ? bit ? and ? repeat? bit ? in ? the ? infoframe ? packet? control ? register ? 1 ? (0x7a:0xc0). ? free datasheet http:///
? ? page ? 19? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide packet handler avi spe mpeg aud new packet? disable repeater bit enable = 0 ? config type, version, length write enable and repeater bits return n y calculate & write checksum load packet data to registers ? ? figure ? 8\ 1?? infoframe ? packets ? configuration ? flowchart ? ? ? ? ? ? ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 20 ? of ? 25 ? preliminary programmer guide 9 hdcp ?authentication ? ANX7150 ? evaluation ? board ? supports ? hdcp ? enable/disable ? by ? setting ? the ? dip ? switch ? #4 ? of ? piano ? switch ? (s10). ? setting ? to ? 1 ? means ? enable ? hdcp, ? and ? setting ? to ? 0 ? means ? disable ? hdcp. ? in ? hdmi ? link ? mode, ? after ? infoframe ? packets ? configuration ? is ? complete, ? the ? firmware? enters ? the ? hdcp ? authentication ? state.? in ? dvi ? link ? mode, ? the ? firmware? enters ? the ? hdcp ? authentication ? state ? when ? video ? configuration ? is ? complete. ? the? ANX7150 ? supports ? two ? hdcp ? authentication ? methods: ? hardware ? hdcp ? authentication ? and ? software ? hdcp ? authentication. ? in ? ANX7150 ? firmware? rev1.0, ? only ? use ? the ? hardware? hdcp ? authentication. ? in ? a? future ? firmware? release, ? the ? software ? hdcp ? authentication ? will ? be ? added ? as ? an ? optional ? feature. ? figure ? 9 \ 1 ? illustrates? the ? initialization ? process ? of ? hdcp ? authentication. ? the ? transmitter ? reads ? the ? bcaps(0x74:0x40) ? and ? bstatus ? register(0x74:0x41 ? and ? 0x74:0x42) ? of ? the ? receiver ? through ? the ? ddc ? channel ? to ? get ? information ? whether ? the ? receiver ? supports ? the ? hdmi ? mode ? and ? the ? hdcp ? 1.1 ? feature. ? ? figure ? 9\ 1??? initialization ? of ? hdcp ? authentication ? free datasheet http:///
? ? page ? 21? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide ? figure ? 9\ 2?? hardware ? hdcp ? authentication ? flowchart ? figure ? 9 \ 2 ? illustrates? the ? hardware ? hdcp ? authentication. ? when ? selecting ? hardware ? method ? for ? hdcp ? authentication, ? the ? firmware? configures ? the ? hard_auth_en ? (0x72:0xa1 ? bit \ 3) ? to ? start ? the ? hdcp ? authentication ? process, ? and ? then ? check ? whether ? bksv ? is ? on ? a? revocation ? list. ? after ? authentication ? completes ? successfully, ? the ? firmware? sets ? hdcp_enc_en ? (0x72:0xa1 ? bit \ 3) ? to ? enable ? hdcp ? encryption. ? bksv? srm? check: ? ksv ? srm ? check ? is ? described ? in ? part ? 5 ? of ? the ? hdcp ? standard. ? the ? ANX7150 ? supports ? bksv ? srm ? check ? performed ? by ? software. ? when ? processing ? the ? bksv_rdy ? (interrupt ? status ? register ? 2 ? 0x72:0x43 ? bit \ 4) ? interrupt, ? the ? firmware? reads ? out ? the ? 5 \ byte ? bksv ? from ? the ? bksv ? register ? 0x72:0xb2~0xb6 ? and ? checks ? whether ? the ? bksv ? is ? on ? a? revocation ? list. ? if ? the ? bksv ? srm ? check ? is ? ok, ? the ? firmware? writes ? bksv_srm_pass ? and ? ksvlist_vld ? (0x72:0xa1 ? bit \ 1 ? and ? bit \ 0)? to ? ?1.? ?? hdcp ? authentication ? monitor ? and ? control: ? when ? processing ? the ? auth_done ? (interrupt ? status ? register ? 2 ? 0x72:0x43 ? bit \ 0)? interrupt, ? the ? firmware? reads ? authen_pass ? (0x72:0xa0 ? bit \ 1) ? and ? determines ? whether ? the ? hardware? authentication ? has ? completed ? properly ? or ? not.? if ? authentication ? passes, ? the ? firmware ? enables ? hdcp ? encryption. ? when ? processing ? the ? auth_state_chg ? (interrupt ? status ? register ? 2 ? 0x72:0x43 ? bit \ 1)? interrupt ? in ? normal ? work ? mode, ? the ? firmware ? reads ? authen_pass ? (0x72:0xa0 ? bit \ 1) ? to ? confirm ? that ? the ? hardware ? authentication ? failed ? and ? then ? to ? disable ? the ? encryption.? hardware ? will ? do ? re\ authentication ? immediately. ? when ? authentication ? failed ? times ? exceeds ? 10, ? the ? firmware? should ? send ? blue ? screen ? until ? authentication ? passes? again. ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 22 ? of ? 25 ? preliminary programmer guide 10 playback ? playback ? is ? the ? normal ? work ? mode ? of ? ANX7150 ? firmware.? when ? entering ? the ? playback ? state, ? if ? avmute ? is ? already ? set, ? the ? firmware? should ? clear ? the ? avmute. ? ? ? 11 interrupt ?process ? the? ANX7150 ? has ? interrupt ? sources ? such ? as ? hotplug ? change, ? video ? format ? change, ? and ? so ? on.? once ? an ? interrupt ? event ? occurs, ? the ? corresponding ? bit ? in ? the ? interrupt ? register ? is ? set. ? when ? firmware? enters ? the ? interrupt ? process ? routine, ? these? bits ? will ? be ? recorded ? and ? cleared, ? and ? then ? the ? corresponding ? interrupt ? will ? be ? handled. ? figure ? 11\ 1, ? figure ? 11\ 2, ? figure ? 11\ 3 ? and ? figure ? 11 \ 4 ? illustrate ? the ? interrupt ? process ? flowchart. ? system state= initial? interrupt process interrupt asserted? system state= waithotplug? hotplug change interrupt a return return y n y n y n ? ? ? \ ?? ? ? ? ? free datasheet http:///
? ? page ? 23? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide a hotplug change interrup video clk change interrupt video format change interrupt audio clock change interrupt bksv ready interrupt hotplug detected? power on chip disable hdcp authentication, video input, audio input, tmds link reset ddc channel read & parse edid state power down chip system state!= initial, wait hotplug, read & parse edid to config video state return y n y n system state!= initial, wait hotplug, read & parse edid to config video state return y n system state!= initial, wait hotplug, read & parse edid disable audio input to config audio state return n y set bksv ready = 1 ? ? figure ? 11\ 2??? interrupt ? process ? flowchart ? (2) ? a authentication done interrupt pll lock change interrupt audio fifo overrun interrupt authentication change interrupt authenticate success? disable blue screen clear srm pass register auth fail count>= 10? auth fail counter ++ send blue screen disable hdcp encryption system state! = initial, wait hotplug, read & parse edid, config video clear srm pass register clear srm pass register return n y n y n y authenticate success? disable blue screen clear srm pass register disable hdcp encryption n y system state = playback? system state!= initial, wait hotplug, read & parse edid disable video disable audio to config video state to hdcp authentication state ? figure ? 11\ 3?? interrupt ? process ? flowchart ? (3) ? free datasheet http:///
? rev ? 0.93 ??????????????????????????????? analogix ? confidential ????????????????????????? page ? 24 ? of ? 25 ? preliminary programmer guide spdif error interrupt system state = initial, wait hotplug, read & parse edid, config video a spdif error counter >= 10? adjust mclk phase parity error? bi phase error? spdif error counter+1 spdif error counter+3 y n y y n y ? figure ? 11\ 4?? interrupt ? process ? flowchart ? (4) ? ? ? ? ? ? ? ? ? ? ? ? ? free datasheet http:///
? ? page ? 25? of ? 25 ??????????????????????????? analogix ? confidential ???????????????????????????? rev ? 0.93 ? preliminary programmer guide ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? copyright ? ?2009 ? analogix ? semiconductor, ? inc ? . ? 3211 ? scott ? blvd., ? suite? 102 ? santa ? clara, ? ca ? 95054, ? usa ? ? (1) ? 408 \ 988 \ 8848 ? ? http://www.analogix.com/ ? ? ? ? ?2009 ?analogix ? semiconductor, ? inc. ?all ? rights? reserved. ? the? information ?contained?in ?this ?document?is ? provided ??as ?is? ? without ?any ? express? representations?of? warranties. ? in ?addition, ?analogix ? semiconductor ?inc. ? disclaims ?all ?implied? representations?and? warranties, ?including ? any ? warranty ?of ? merchantability, ? fitness ? for?a? particular ? purpose, ? or ?non\ infringement ?of?third ? party ?intellectural? property? rights. ?specification ?is ? subject ?to ? change ? without ? notice. ?? this ?document ? contains ?proprietary ? information ?of ? analogix ?semiconductor, ? inc. ?or ? under ? license ? from ? third ? parties. ?no ?part ?of ?this ? document ?may ?be ? reproduced ?in ?any ? form ?or ?by ?any ? means ?or ? transferred ? to ?any ? third ?party ? without ?the ?prior ? written ? consent ? of ? analogix ? semiconductor, ? inc. ? the ? information?contained?in ?this ?document ?is ?not ?designed ?or ?intended ?for ? use ?in ?on \ line ? control ?of ? aircraft, ? aircraft ? navigation ?or ? aircraft ? communications; ?or ?in ?the ?design, ? construction, ? operation ?or ? maintenance ?of ?any ? nuclear ? facility. ? analogix ? disclaims ?any ? express?or ? implied ? warranty ?of ?fitness ?for ? such ? uses. ?? analogix ? semiconductor, ? inc., ?the ? analogix ?logo, ?and? wideeye? ? serdes, ?and? cool hd ? ? are ? trademarks ?of ? analogix ? semiconductor,? inc., ? in ?the ? united ?states ?and?other ? countries. ? hdmi, ?the ?hdmi ?logo ?and?high \ definition ? multimedia ? interface ?are ? trademarks ?or ? registered ? trademarks ? of ? hdmi ?licensing ?llc. ? displayport ?and?the ?displayport ?logo ? are ? trademarks ?or ? registered ? trademarks ? of ?the ? video ? electronics ?standards ?association, ? vesa?. ? all ?other ? trademarks ?and? registered ? trademarks ? are ?the ? property ?of ?their ? respective ? owners. ? free datasheet http:///

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